1. Field of the Invention
The present invention relates to a process for fabricating integrated devices including flash-EEPROM memories and transistors.
2. Discussion of the Related Art
Flash-EEPROM memories are Electrically Erasable Programmable Read Only Memories (EEPROMs) which combine the high density and low cost of EPROMs, with the advantage of electrical erasability. These memories have recently become the most attractive of the nonvolatile memories for their potential application in solid state disks for portable computers.
Although different flash memory concepts have been developed, most flash manufacturers utilize a double-poly single-transistor cell which is very similar to a standard EPROM cell.
FIGS. 1 and 2 are cross-sectional views of EPROM and flash-EEPROM cells, respectively. As shown in FIG. 1, an EPROM cell, indicated as a whole by 1, is formed in a P-type substrate 2, having N+ type source and drain regions 3 and 4, respectively, separated by a channel region 5 formed by the substrate itself. Over substrate 2, at channel 5, two gate regions are provided: a floating gate region 6 completely embedded in an oxide layer 8, and a control gate region 7. Gate region 6 is made of polycrystalline silicon; gate region 7 may be polysilicon or polycide (polysilicon and silicide). The floating gate region is separated from the substrate by an oxide layer (gate oxide) 8a of a given thickness (typically 200 Angstroms).
As shown in FIG. 2, a flash-EEPROM cell, indicated as a whole by 15, is very similar to the EPROM cell shown in FIG. 1, and is formed in a P-type substrate 16, having source and drain regions 17 and 18, respectively, separated by a channel 19. A floating gate region 20, and a control gate region 21, both surrounded by an oxide layer 22, are provided. As compared with EPROM cell 1, however, the oxide layer 22a, which separates floating gate region 20 from substrate 16, is known as the tunnel oxide and is much thinner than oxide layer 8a, typically 100-130 A. In the specific embodiment shown, source region 17 has a graded junction with the substrate, and is formed in two parts: a heavily doped (N+) part 17a facing the larger surface 23 of the substrate, and a deeper, lightly doped (N-) part 17b surrounding part 17a on the sides not facing surface 23.
The purpose of a graded junction is to enable the cell to better withstand the electrical stress to which it is subjected during erasing and programming, and may or may not be provided, depending on the operating conditions of the memory array. The thin tunnel oxide layer, on the other hand, is essential for enabling electronic erasing (and programming) of the cell by Fowler-Nordheim tunneling between the substrate and floating gate.
Due to its limited thickness, flash-EEPROM fabrication involves specific steps for forming the tunnel oxide layer, thus ruling out direct application of standard EPROM processes.
The present applicant has developed and patented an EPROM process whereby the second polysilicon layer is deposited directly on the first in the circuit transistor area for forming the gate regions of the transistors. This process, unlike other known processes, does not require removal of the first polysilicon layer in the circuit area. This process, which is discussed in U.S. Pat. No. 4,719,184 issued Jan. 12, 1988, is known as DPCC (Shorted Double Poly) and provides advantages of reliability and in the number of masks required.